CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

I²C CONTROL PORT SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD; SDA CL = 30 pF.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 17)

thdd

10

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc

-

Fall Time SCL and SDA

tfc

-

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

tack

300

100

kHz

-

ns

-

µs

-

µs

-

µs

-

µs

-

µs

-

ns

-

ns

1

µs

300

ns

-

µs

1000

ns

Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

RST

t irs

Stop

Start

Repeated

Start

SDA

t buf

t hdst

t high

t hdst

tf

SCL

t low t hdd

t sud

t sust

tr

Figure 11. Control Port Timing - I²C

Stop

t susp

24

DS726PP3

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