CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

AUX SERIAL AUDIO I/O PORT SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; AUX_SDOUT & DLY_SDOUT CL = 15 pF; Inputs:

Logic 0 = DGND; Logic 1 = VD; (Note 11).

Parameters

Symbol

Min

Typ

Max

Units

Input Source: Analog Inputs (Internal ADC)

Output Sample Rate

(Note 16)

AUX_LRCK Duty Cycle

ClkFreq[1:0] = ‘00’

ClkFreq[1:0] = ‘01’ FSO

ClkFreq[1:0] = ‘10’

-

FCLK/384

-

Hz

-

FCLK/512

-

Hz

-

FCLK/512

-

Hz

-

50

-

%

AUX_LRCK Period

AUX_SCLK Frequency

(Note 16)

AUX_SCLK Duty Cycle

-

1/FSO

-

s

ClkFreq[1:0] = ‘00’

-

48*FSO

-

Hz

ClkFreq[1:0] = ‘01’ FSCLKO

-

64*FSO

-

Hz

ClkFreq[1:0] = ‘10’

-

64*FSO

-

Hz

-

50

-

%

AUX_SCLK Period

Input Source: Serial Audio Input Port

-

1/FSCLKO

-

s

Output Sample Rate

FS-In = 32kHz, 44.1 kHz, 48 kHz

FS-In = 96 kHz

FSO

-

-

AUX_LRCK Duty Cycle

(Note 13)

45

FSI

FSI/2

-

-

Hz

-

Hz

55

%

AUX_LRCK Period

AUX_SCLK Frequency

(Note 14)

(Note 12, 13)

FS-In = 32kHz, 44.1 kHz, 48 kHz

FS-In = 96 kHz

TSI - TCLK

TSI

TSI + TCLK

s

-

FSCLKI

-

Hz

-

FSCLKI/2

-

Hz

AUX_SCLK Duty Cycle

30

-

70

%

AUX_SCLK Period

(Note 13, 14)

FS-In = 32kHz, 44.1 kHz, 48 kHz

FS-In = 96 kHz

TSCLKI - TCLK

TSCLKI

TSCLKI + TCLK

s

2*TSCLKI - TCLK 2*TSCLKI 2*TSCLKI + TCLK s

Input Source: Analog Inputs or Serial Audio Input Port

AUX_LRCK Rising Edge to AUX_SCLK Falling Edge

tLTSF

-

AUX_SCLK Rising Edge to Data Output Valid

tSRDV

-

DLY_SDIN Setup Time Before AUX_SCLK Rising Edge

tDIS

25

DLY_SDIN Hold Time After AUX_SCLK Rising Edge

tDIH

10

-

20

ns

-

TCLK + 20

ns

-

-

ns

-

-

ns

Notes:

11. FCLK is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal.

TCLK = 1/FCLK.

12. FSI is the frequency of the input LRCK signal. TSI = 1/FSI

13. May vary during normal operation.

14. FSCLKI is the frequency of the input SCLK signal. TSCLKI = 1/FSCLKI.

AUX_LRCK

AUX_SCLK

AUX_SDOUT

DLY_SDOUT

LSB

tDISU

DLY_SDIN LSB

tLTSF

MSB

MSB

tSRDV

MSB - 1

tDIH

MSB - 1

Figure 8. AUX Serial Port Interface Master Mode Timing

22

DS726PP3

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