CS5542 查看數據表（PDF） - Cirrus Logic

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CS5542

22-Bit, Multi-Channel ∆Σ ADC Chip Set

Cirrus Logic 

CS5542 CS5543

CS5543 PIN DESCRIPTIONS

CAL[1:0] - Calibration Control (Outputs), Pins 8, 9.

The mode of operation for the CS5542 is selected through the calibration Control pins. See the

table in the pin-out section of the CS5542 data sheet for details.

FSYNC - Frame Sync (Output), Pin 10.

The transition from a low to high level at the CS5542’s input will reset the internal master

timing of the CS5542 and synchronize its data with each output word from the CS5543.

MCLK - Modulator Clock (Output), Pin 11.

The modulator clock output provides the necessary clock for operation of the modulator.

CAPSIZE - Full Scale Input Range Select (Output), Pin 14.

Controls the CAPSIZE input to the CS5542. This determines the size of the sampling capacitor

used by the CS5542.

PDN - Power Down (Output), Pin 15.

When asserted the CS5542 will enter the power-down state.

MDATA[3:0] - Modulator Data Inputs (Inputs), Pins 16, 17, 18, 19.

The tri-level modulator data is input to the CS5543 via MDATA3 - MDATA0 for decimation.

See the table in the pin-out section of the CS5542 data sheet for details.

Test Access Port Pins

TMS -Test Mode Select (Input), Pin 20.

Controls the state-to-state operation of the TAP controller.

TDI - Test Data Input (Input) , Pin 21.

Serially inputs data to the Test Access Port.

TDO - Test Data Output (Output), Pin 22.

Serially outputs data from the Test Access Port.

TCK - Test Clock (Input), Pin 23.

The clock for the Test Access Port, shorted to MCLK

Control Pins

OE - Output Enable (Input), Pin 27.

Enables or disables (tri-states) all output pins on the CS5543.

FEGAIN - Front-End Gain Select (Input), Pin 28.

Selects the Front-End Capacitor Gain Ratio. A full calibration is necessary following any

change to this input.

DS109PP2

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