CS5542 查看數據表（PDF） - Cirrus Logic

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CS5542

22-Bit, Multi-Channel ∆Σ ADC Chip Set

Cirrus Logic 

CS5542 CS5543

CS5542 PIN DESCRIPTIONS

DGND - Digital Ground, Pin 22.

Digital ground.

Digital Input Pins-

MCLK - Modulator Clock Input, Pin 17.

The modulator clock input provides the necessary clock for operation of the modulator. MCLK

operates at 16 times the modulator sample rate. MCLK is 2048 times the output word rate.

FSYNC - Frame Sync, Pin 16.

The transition from a low to high level on this input supplied by the CS5543, will reset the

internal master timing of the CS5542 and synchronize its data with each output word.

CAL[1:0] - Calibration Control, Pins 19, 18.

The mode of operation for the CS5542 is selected through the calibration control pins via the

CS5543 and is summarized in the table below.

CAL1

CAL0

Mode Selected

0

0

Normal Operation, Noise CAL, Offset CAL

0

1

Input offset voltage calibrate

1

0

Unused code

1

1

Full Scale gain calibrate

Normal Calibration Sequence

01

Input Offset

00

Noise CAL(Dark)

00

Offset CAL(Dark)

11

Gain CAL

00

Normal Operation

SEL[1:0] - Time Slot Selections, Pins 15,14

The binary code applied to SEL0 and SEL1 will determine the time slot pair associated with

the CS5542. Each of the up to four CS5542’s connected to a single CS5543 must have a unique

code assigned to the combination of SEL0 and SEL1.

CAPSIZE - Full Scale Input Range Select, Pin 1.

When CAPSIZE = 0, CDAC = 1.6 pF; when CAPSIZE = 1, CDAC = 4.8 pF

24

DS109PP2

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