CS8900 데이터 시트보기 (PDF) - Cirrus Logic
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CS8900 Datasheet PDF : 132 Pages
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4.6 Address Filter Registers
CS8900
Address Filter Register:
Logical Address Filter (hash table) (Read//Write)
Address: PacketPage base + 0150h
Address 0157h Address 0156h Address 0155h Address 0154h Address 0153h Address 0152h Address 0151h Address 0150h
Most-
significant
byte of hash
filter.
Least-
significant
byte of hash
filter.
The CS8900 hashing decoder circuitry compares its output with one bit of the Logical Address Filter Register. If
the decoder output and the Logical Address Filter bit match, the frame passes the hash filter and the Hashed bit
(Register 4, RxEvent, Bit 9) is set. See Section 5.3.
This register’s initial state after reset is:
0000 0000 0000 0000 0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Address Filter Register:
Individual Address (IEEE address) (Read//Write)
Address 0015Dh Address 0015Ch Address 0015Bh
High-order byte of IA
Address: PacketPage base + 0158h
Address 0015Ah
Address 0159h
Address 00158h
Low-order byte of IA.
The unique, IEEE 48-bit Individual Address (IA) begins at 0158h. The first bit of the IA (Bit IA[00]) must be "0".
See Section 5.3. The bit ordering for the IA is:
PacketPage
Address
0158h
0159h
015Ah
015Bh
015Ch
015Dh
Most-Significant Bit of
IA in this byte
IA[47]
IA[39]
IA[31]
IA[23]
IA[15]
IA[07]
Most-Significant Bit of
IA in this byte
IA[40]
IA[32]
IA[24]
IA[16]
IA[08]
IA[00]
The value of this register must be loaded from external storage, for example, from the EEPROM. See Section
3.3. If the CS8900 is not able to load the IA from the EEPROM, then after a reset this register is undefined, and
the driver must write an address to this register.
70
DS150PP2
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