CS8900 데이터 시트보기 (PDF) - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register 1C: AUI Time Domain Reflectometer (Read-only)

Address: PacketPage base + 013Ch

F-6

AUI_Delay

5-0

011100

The TDR counter (Bits 6 through F) is a time domain reflectometer useful in locating cable faults in 10BASE-2

and 10BASE-5 coax networks. It counts at a 10 MHz rate from the beginning of transmission on the AUI to when

a collision or Loss-of-Carrier error occurs. The TDR counter is cleared when read.

BIT NAME

DESCRIPTION

5-0 011100

These bits provide an internal address used by the CS8900 to identify this as the Bus

Status Register. When reading this register, these bits will be 011100, where the LSB

corresponds to Bit 0.

F-6 AUI-Delay

The upper ten bits contains the number of 10 MHz clock periods between the

beginning of transmission on the AUI to when a collision or Loss-of-Carrier error

occurs.

This register’s initial state after reset is: 0000 0000 0001 1100

DS150PP2

67

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