CS8900 데이터 시트보기 (PDF) - Cirrus Logic
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CS8900 Datasheet PDF : 132 Pages
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CS8900
Register 19: Test Control (TestCTL, Read/Write)
F
E
D
FDX
C
B
A
9
Disable
Backoff
AUIloop
ENDEC
loop
TestCTL controls the diagnostic test modes of the CS8900.
Address: PacketPage base + 0118h
8
7
6
DisableLT
5-0
011001
BIT NAME
5-0 011001
7
DisableLT
9
ENDECloop
A
AUIloop
B
Disable
Backoff
E
FDX
F
FastTest
DESCRIPTION
These bits provide an internal address used by the CS8900 to identify this as the Test
Control Register. To write to this register, these bits must be 011001, where the LSB
corresponds to Bit 0.
When set, the 10BASE-T interface allows packet transmission and reception regardless
of the link status. DisableLT is used in conjunction with the LinkOK (Register 14,
LineST, Bit 7) as follows:
LinkOK
0
DisableLT
0
No packet transmission nor reception
allowed. Transmitter sends link pulses.
0
1
DisableLT overrides LinkOK to allow
packet transmission and reception.
Transmitter does not send link pulses.
1
N/A
DisableLT has no meaning if LinkOK = 1.
Note that if the receiver is receiving no link pulses, then the 10BASE-T transmitter can
be active only if bit DisableLT is set.
When set, the CS8900 enters internal loopback mode where the internal Manchester
encoder output is connected to the decoder input. The 10BASE-T and AUI transmitters
and receivers are disabled. When clear, the CS8900 is configured for normal operation.
When set, the CS8900 allows reception while transmitting. This facilitates loopback tests
for the AUI. When clear, the CS8900 is configured for normal AUI operation.
When set, the backoff algorithm is disabled. The CS8900 transmitter looks only for
completion of the inter packet gap before starting transmission. When clear, the backoff
algorithm is used.
When set, 10BASE-T full duplex mode is enabled and CRS (Register 14, LineST, Bit E)
is ignored. This bit must be set when performing loopback tests on the 10BASE-T port.
When clear, the CS8900 is configured for standard half-duplex 10BASE-T operation.
When set, internal counters and timers are scaled in order to speed-up chip testing.
When clear, normal timing is used.
At reset, if no EEPROM is found by the CS8900, then the register has the following initial state. If an EEPROM is
found, then the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0001 1001
66
DS150PP2
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