CL-PS7111-VC-A データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

Table 5-1. Internal I/O Memory Locations in Little-Endian Mode (cont.)

Address Name Default R/W Size

Comments

Page

8000.00C0 PEDDR

0

8000.0100 SYSCON1

0

8000.0140 SYSFLG1

0

8000.0180 MEMCFG1

0

8000.01C0 MEMCFG2

0

8000.0200 DRFPR

0

8000.0240 INTSR1

0

8000.0280 INTMR1

0

8000.02C0 LCDCON

0

8000.0300

TC1D

0

8000.0340

TC2D

0

8000.0380 RTCDR

–

8000.03C0 RTCMR

–

8000.0400 PMPCON

0

8000.0440

CODR

0

8000.0480 UARTDR1

0

8000.04C0 UBRLCR1

0

8000.0500 SYNCIO

0

8000.0540 PALLSW

0

8000.0580 PALMSW

0

8000.05C0 STFCLR

–

8000.0600

BLEOI

–

8000.0640 MCEOI

–

8000.0680

TEOI

–

8000.06C0 TC1EOI

–

8000.0700 TC2EOI

–

8000.0740 RTCEOI

–

8000.0780 UMSEOI

–

8000.07C0 COEOI

–

8000.0800

HALT

–

8000.0840 STDBY

–

RW 3 Port E Data Direction register

47

RW 21 System Control register 1

48

R

32 System Status Flags register 1

50

RW 32 Expansion and ROM Memory Configuration register 1

53

RW 32 Expansion and ROM Memory Configuration register 2

54

RW 8 DRAM Refresh Period register

57

R

32 Interrupt Status register 1

58

RW 32 Interrupt Mask register 1

60

RW 32 LCD Control register

60

RW 16 Read/write data to Timer Counter 1 Data register

62

RW 16 Read/write data to Timer Counter 2 Data register

62

RW 32 Realtime Clock Data register

62

RW 32 Realtime Clock Match register

62

RW 12 DC-to-DC Converter Pump Control register

63

RW 16 Codec Interface Data register

64

RW 8/11 UART FIFO Data register 1

64

RW 32 UART Bit Rate and Line Control register

65

RW 16 Synchronous Serial I/O Data register only for Master SSI 67

RW 32 Least-significant 32-bit word of LCD Palette register

68

RW 32 Most-significant 32-bit word of LCD Palette register

68

W

– Write to clear all start up reason flags

69

W

– Write to clear Battery Low interrupt

69

W

– Write to clear Media Changed interrupt

69

W

– Write to clear Tick and Watchdog interrupt

69

W

– Write to clear TC1 interrupt

69

W

– Write to clear TC2 interrupt

69

W

– Write to clear RTC Match interrupt

69

W

– Write to clear UART Modem Status Changed interrupt

69

W

– Write to clear Codec Sound interrupt

69

W

– Write to enter idle state

69

W

– Write to enter standby state

69

September 1997

PRELIMINARY DATA BOOK v2.0

45

REGISTER DESCRIPTIONS

Share Link: