CL-PS7111-VC-A データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

PSLEEP pin of the CL-PS6700, allowing them to be put into a power saving state before the CL-PS7111

enters standby mode.

NOTE: It is essential that the software monitors the appropriate status registers within the CL-PS6700 to ensure no

pending posted bus transactions before standby mode is entered. Failure to do this will result in incomplete

PCMCIA accesses.

3.9 DRAM Controller

The DRAM controller in the CL-PS7111 allows all connections to directly interface up to two banks of

DRAM. The width of the memory interface is programmable to 16-bit or 32-bit. The two banks have to be

the same width. Each bank can be up to 256 Mbytes. Two RAS lines and four CAS lines are provided, one

CAS line per byte line. CAS0 enables D[7:0] in little-endian as well as big-endian modes. The DRAM

device size is not programmable. Therefore, devices used that are smaller than the largest size supported

(1-Gbit), lead to a segmented memory map, each bank being separated by 256 Mbytes. Segments

smaller than the bank size repeat within the bank. Table 3-9 shows the mapping of physical address-to-

DRAM row and column address. This mapping has been organized to support any DRAM device size

from 4--Mbit to 1-Gbit with a ‘square’ row and column configuration (the number of column addresses

equals the number of row addresses). If a non-square DRAM is used, further fragmentation of the mem-

ory map can occur, although the smallest contiguous segment is always 1-Mbyte. With proper mapping

of pages and sections by the MMU, contiguous memory blocks can be created.

The DRAM controller breaks all sequential access that the minimum page sizes defined support.

Table 3-9. Physical-to-DRAM Address Mapping

Memory

Address

DRAM

Column

×16 mode

DRAM

Column

×32 mode

0

A1 a

A2

1

A2

A3

2

A3

A4

3

A4

A5

4

A5

A6

5

A6

A7

6

A7

A8

7

A8

A9

8

A18

A19

9

A20

A21

10

A22

A23

11

A24

A25

12

A26

A27

a This bit will be generated by the DRAM controller.

DRAM Row DRAM Row

×16 mode ×32 mode

Pin Name

A9

A10

A27/DRA0

A10

A11

A26/DRA1

A11

A12

A25/DRA2

A12

A13

A24/DRA3

A13

A14

A23/DRA4

A14

A15

A22/DRA5

A15

A16

A21/DRA6

A16

A17

A20/DRA7

A17

A18

A19/DRA8

A19

A20

A18/DRA9

A21

A22

A17/DRA10

A23

A24

A16/DRA11

A25

A26

A15/DRA12

30

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

Share Link: