CL-PS7111-VC-A データシートの表示（PDF） - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

The codec is enabled when SYSCON2[0] is high. On power-up, this bit is reset low so that the codec is

disabled.Table 3-16 shows the pin assignments for the serial interface.

Table 3-16. Serial Interface Pin Assignments

Pin Name

PCMCLK

PCMSYNC

PCMOUT

PCMIN

Type Codec Functionality

I/O PCMCLK serial shift clock

O PCMSYNC output frame sync

O PCMOUT serial output data

I PCMIN serial input data

3.16.1 Codec Interface

The codec interface allows a direct connection of a telephony-type codec to the CL-PS7111, providing all

the necessary clocks and timing pulses and performing serialization of the data stream to/from the exter-

nal codec. The interface is full-duplex and contains two separate data FIFOs (16- deep by 8-bits wide, one

for receive data, another for transmit data).

Data is transferred to/from the codec at 64 kbps, either written to or read from the appropriate 16-byte

FIFO. The sound interrupt is generated every 8 bytes transferred (FIFO half full/empty), which means the

interrupt rate is 1 kHz with a latency of 1 ms.

NOTE: Both CDENRX and CDENTX must be enabled to receive or transmit, and upon completion of transmit the

speaker amplifier should be turned off to avoid audible noise. This is required because CL-PS7111 transmits

and receives data in FIFO.

3.16.2 ADC Interface — Master-Mode Only SSI (Synchronous Serial Interface)

The first synchronous serial interface allows peripheral devices (such as ADCs, that have an SPI1 or

Microwire2 compatible interface) to be directly connected to the CL-PS7111. The clock output frequency

is programmable and is only active during data transmissions to save power. There are four output fre-

quencies available, differing slightly between 13-MHz and 18.432-MHz mode (see Table 3-17). The

required frequency is selected by programming the corresponding bits (16 and 17) in the SYSCON1 reg-

ister. The sample clock (SMPCLK) always runs at twice the frequency of the shift clock (ADCCLK).

Table 3-17. ADC Interface Operation Frequencies

SYSCON1[16] SYSCON1[17]

0

0

0

1

1

0

1

1

13.0-MHz Operation

ADCCLK

Frequency (kHz)

4.2

16.9

67.7

135.4

18.432-MHz Operation

ADCCLK

Frequency (kHz)

4

16

64

128

1 SPI is a registered trademark of Motorola™.

2 Microwire™ is a registered trademark of National Semiconductor.

September 1997

PRELIMINARY DATA BOOK v2.0

41

FUNCTIONAL DESCRIPTION

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