CS493254-CLZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS493254-CLZ Datasheet PDF : 90 Pages
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CS49300 Family DSP
more detailed description of the different hardware
configurations can be found in Section 11,
“Hardware Configuration” on page 74.
The software configuration messages are specific
to each application. The software user’s guides
(AN163, AN163x, AN162, AN162x) for each
application code provides a list of all pertinent
configuration messages. Writing the KICKSTART
message to the CS493XX begins the audio
decode process. The KICKSTART message will
also be described in the user’s guide for each
application. Until the KICKSTART has been sent,
the decoder is in a wait state.
8.2.1. Autoboot INTREQ Behavior
It is important to note that ABOOT and INTREQ
are multiplexed on pin 20 of the CS493XX.
Because this pin serves as an input before reset,
and an output after reset, the host should release
the ABOOT line after RESET has gone high. As
shown in Figure 37, "Autoboot INTREQ Behavior"
on page 60, the host must drive ABOOT low
around the rising edge of RESET.
After the host has released the ABOOT line, it will
remain high while the DSP prepares to load code
from the external memory. INTREQ should be
ignored during download, i.e. interrupts should be
masked on the host. The download time will vary
according to the size of the download image and
the frequency of the main DSP clock. The autoboot
sequence is specified to complete within 200 ms
(from the rising edge of RESET). Note: This time
has been tested using the ac3_493263_13.ld
application code release, however other
application code releases MAY take longer than
200mS as they have may an increased image size
and may take longer to initialize all of the internal
state variables. It is up to the designer to verify the
actual times required for each application code in
their system.
RESET
ABOOT
60
Trstsu
Driven Low by Host
Driven Low by CS492X
Download in Progress
Trsthld
Figure 37. Autoboot INTREQ Behavior
DS339F7
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