CS493254-CLZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS493254-CLZ

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

The timing for an autoboot sequence is illustrated

in Figure 35. The sequence is initiated by driving

RESET low and placing the decoder into reset. At

the rising edge of RESET, the ABOOT, WR, and

RD pins are sampled. If ABOOT is low when

sampled, and the WR and RD pins are set to

configure the device for serial communications, the

device will begin to autoboot (PSEL is a don’t care

for serial communications modes). Section 6.1,

“Serial Communication” on page 36 discusses the

procedure required for placing the CS493XX into a

serial communication mode in more detail. For a

more thorough description of ABOOT’s behavior

after the rising edge of RESET please refer to

Section 8.2.1, “Autoboot INTREQ Behavior” on

page 60

The EMOE pin of the CS493XX is used for two

purposes. It generates clock pulses for the latches,

and it is used in conjunction with EXTMEM to

enable the outputs of the ROM. The first three

rising edges of EMOE are used to latch address

bytes, as shown in the diagram. The fourth low

pulse of EMOE is used to enable the ROM outputs.

When both EXTMEM and EMOE go low, the

EMAD[7:0] pins of the DSP become inputs and

await the data coming from the ROM.

When comparing the memory system in Figure 30,

"External Memory Interface" on page 53 to the

timing diagram of Figure 35, "Autoboot Timing

Diagram" on page 58 there may appear to be a

discrepancy. The timing diagram shows three

address cycles, but there are only two latches in

the illustration of the memory architecture. This

difference is a result of code size limitations. The

application code is guaranteed to fit into a 32

Kilobyte space, which means that only 15 address

bits will actually be used for retrieving code from

the ROM. Thus, the two latches catch the least

significant bytes, and the most significant byte is

dropped.

In autoboot mode, latching the most significant

byte would be perfectly valid since the most

significant bits are guaranteed to be zeros (the

three bytes represent a true 24-bit address).

The flow chart given in Figure 36, "Autoboot

Sequence" on page 59 demonstrates the

interaction required by the microcontroller when

placing the DSP into autoboot mode. The host

must first drive the RESET line low.

After waiting for 175 ms, the application code

should be fully downloaded to the DSP, however

the designer should note that this time is typical

and may vary for each application code. During the

wait period, the host should ignore all INTREQ

behavior (mask the INTREQ interrupt). The host

can then verify that the code has successfully

initialized itself by sending a solicited read

command to the DSP to check for a known default

value. For example, by sending

Rd_Audio_Mgr_Request (0x090003) the host will

receive Rd_Audio_Mgr_Response (0x890003,

0x000000). If the first read attempt returns an

incorrect value, a 5ms wait should be inserted and

the read should be repeated. If a second invalid

response is read, the entire boot process should

then be repeated. When the number returned

matches the default value for the variable read, the

host can be confident that the application is

resident in the DSP and awaiting further

instructions. An application code user’s guide

should be consulted for information about reading

a variable from the part.

Hardware configuration messages are used to

define the behavior of the DSP’s audio ports. A

RESET

ABOOT

EXTMEM

EMOE

EMWR

EMAD7:0

MA23:16 MA15:8

MA7:0

Figure 35. Autoboot Timing Diagram

Data7:0

58

DS339F7

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