CS493254-CLZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS493254-CLZ

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

RESET(LOW) (NOTE 1)

READ HOSTCTL

REGISTER

RESET(HIGH) (NOTE 2)

N

HOUTRDY LOW?

Y

READ_*(MESSAGE)

TIMEOUT AFTER

20MS (NOTE 3)

MESSAGE ==

N

BOOTSTART?

Y

WRITE_*(.LD FILE,

DOWNLOAD FILE SIZE)

READ HOSTCTL

REGISTER

EXIT(ERROR)

N

HOUTRDY LOW?

Y

READ_*(MESSAGE)

MESSAGE ==

N

BOOT_SUCCESS?

Y

WRITE_*(BOOT_

SUCCESS_RECEIVED,

MSG-SIZE)

WAIT 5 MS (NOTE 4)

TIMEOUT AFTER

20MS (NOTE 3)

EXIT(ERROR)

WAIT 500 µs

WRITE_*(DOWNLOAD_

BOOT, MSG_SIZE)

Notes: 1. RESET must be held LOW for

trstl.

2. It should be noted that mode

pins are used to configure the

CS493XX serial communication

mode. These mode pins are

latched internally on the rising

edge of reset. The pins can be

set dynamically by a

microprocessor or can be

statically pulled HIGH or LOW. If

these pins are driven

dynamically, setup and hold

times must be satisfied as stated

in the CS493XX Data Sheet.

More information about the

function of the mode pins can be

found in the CS493XX Data

Sheet and in Section 6, “Control”

on page 36.

3. Time-out values reflect worst

case response time for the

CS493XX. The values shown

may be used for the host’s time-

out control loop.

4. 5 ms is typical but this time is

application code specific and

may be as high as 10 ms. Wait

times should be verified by the

designer.

5. Hardware configuration

messages are covered in

Section 6, “Control” on page 36.

Application configuration

messages are covered in each

application code user’s manual.

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WRITE_*(HW_CONFIG_MSG,

HW_MSG_SIZE)

(NOTE 5)

WRITE_*(SW_CONFIG_MSG,

SW_MSG_SIZE)

(NOTE 5)

WRITE_*(KICKSTART,

MSG_SIZE)

(NOTE 5)

Figure 34. Typical Parallel Boot and Download Procedure

56

DS339F7

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