CRD8900-1 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CRD8900-1

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

that it extends the maximum time needed to gain clock and NRZ data from incoming Manchester-

access to the network for the first three re-tries.

encoded data.

The host may choose to disable the Backoff al-

gorithm altogether by setting the DisableBackoff

bit (Register 19, TestCTL, Bit B). When dis-

abled, the CS8900 only waits the 9.6 µs IPG

time before starting transmission.

Figure 3.9 provides a block diagram of the EN-

DEC and how it interfaces to the MAC, AUI and

10BASE-T transceiver.

Encoder

SQE Test: If the CS8900 is transmitting on the

AUI, the external transceiver should generate an

SQE Test signal on the CI+/CI- pair following

each transmission. The SQE Test is a 10 MHz

signal lasting 5 to 15 bit times and starting

within 0.6 to 1.6 µs after the end of transmis-

sion. During this period, the CS8900 ignores

receive carrier activity (see SQE Error in this

section for more information).

3.10 Encoder/Decoder (ENDEC)

The CS8900’s integrated encoder/decoder (EN-

DEC) circuit is compliant with the relevant

portions of section 7 of the Ethernet standard

(ISO/IEC 8802-3, 1993). Its primary functions

include: Manchester encoding of transmit data;

informing the MAC when valid receive data is

present (Carrier Detection); and, recovering the

The encoder converts NRZ data from the MAC

and a 20 MHz Transmit Clock signal into a se-

rial stream of Manchester data. The Transmit

Clock is produced by an on-chip oscillator cir-

cuit that is driven by either an external 20 MHz

quartz crystal or a TTL-level CMOS clock input.

If a CMOS input is used, the clock should be 20

MHz ±0.01% with a duty cycle between 40%

and 60%. The specifications for the crystal are

described in section 13.0 (Quartz Crystal Re-

quirements). The encoded signal is routed to

either the 10BASE-T transceiver or AUI, de-

pending on configuration.

Carrier Detection

The internal Carrier Detection circuit informs the

MAC that valid receive data is present by assert-

ing the internal Carrier Sense signal as soon it

detects a valid bit pattern (1010b or 0101b for

Carrier Sense

RX CLK

MAC

RX NRZ

TXCLK

TX NRZ

TEN

Port Select

Collision

ENDEC

Carrier

Detector

Decoder

& PLL

RX

MUX

Encoder

TX

MUX

Clock

Figure 3.9. ENDEC

RXSQL

10BASE-T

RX

Transceiver

TX

AUISQL

AUIRX

AUITX

AUI

AUICol

30

DS150PP2

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