CRD8900-1 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CRD8900-1

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

1. Issue an Erase/Write Enable command.

2. Load the data into the EEPROM Data register.

3. Issue a Write command.

4. Issue an Erase/Write Disable command.

During the Erase command, the CS8900 writes

FFh to the specified EEPROM location. During

the Erase-All command, the CS8900 writes FFh

to all locations.

3.6 Boot PROM Operation

The CS8900 supports an optional Boot PROM

used to store code for remote booting from a

network server.

Accessing the Boot PROM

To retrieve the data stored in the Boot PROM,

the host issues a Read command to the Boot

PROM as a Memory space access. The CS8900

decodes the command and drives the CSOUT

pin low, causing the data stored in the Boot

PROM to be shifted into the bus transceiver. The

bus transceiver then drives the data out onto the

ISA bus.

CS8900

CSOUT

(Pin 17)

27C256

20

CE

22 OE

SA(0:14)

74LS245

19

OE

DIR

A1

.

B1

.

. SD(0:7)

.

.

A8

.

B8

ISA

BUS

Figure 3.3. Boot PROM Connection Diagram

Configuring the CS8900 for Boot PROM

Operation

Figure 3.3 show how the CS8900 should be con-

nected to the Boot PROM and ’245 driver. To

configure the CS8900’s internal registers for

Boot PROM operation, the Boot PROM Base

Address must be loaded into the Boot PROM

Base Address register (PacketPage base + 0030h)

and the Boot PROM Address Mask must be

loaded into the BootPROM Address Mask regis-

ter (PacketPage base + 0034h). The Boot PROM

Base Address provides the starting location in

host memory where the Boot PROM is mapped.

The Boot PROM Address Mask indicates the

size of the attached Boot PROM and is limited

to 4-Kbyte increments. The lower 12 bits of the

Address Mask are ignored and should be 000h.

In the EEPROM example shown in Table 3.6,

the Boot PROM starting address is D0000h and

the Address Mask is FC000h. This configuration

describes a 16-Kbyte (128 Kbit) PROM mapped

into host memory from D0000h to D3FFFh.

3.7 Low-Power Modes

For power-sensitive applications, the CS8900

supports three low-power modes: Hardware

Standby, Hardware Suspend, and Software Sus-

pend. All three low-power modes are controlled

through the SelfCTL register (Register 15). See

also Section 5.85.8.

An internal reset occurs when the CS8900 comes

out of any suspend or standby mode. After a re-

set (internal or external), the CS8900 goes

though a self configuration. This includes cali-

brating on-chip analog circuitry, and reading

EEPROM for validity and configuration. When

the calibration is done, bit InitD in Register 16

(Self Status register) is set indicating that initiali-

zation is complete, and the SIBusy bit in the

same register is cleared (indicating that the

EEPROM is no longer being read or pro-

22

DS150PP2

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