CS8900 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8900 Datasheet PDF : 132 Pages
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CS8900
Input Cycle
During the Input Cycle, the falling edge of AEN
causes the state of each selected pin to be trans-
ferred to EEDataOut (that is, EEDataOut will be
high or low depending on the input level of the
selected pin). This cycle begins with SLEEP
and advances clockwise through each of 33 input
pins (all digital input pins except for AEN) and
each of the 17 bi-directional pins, one pin at a
time.
The following is a list of input pins and bi-direc-
tional pins that are tested during the Input Cycle:
Pin Name
ELCS
EEDataIn
CHIPSEL
DMACK2
DMACK1
DMACK0
SD08-SD15
MEMW
MEMR
Pin #
2
6
7
12
14
16
27-24,21-18
28
29
Pin Name
SBHE
SA0 - SA11
REFRESH
SA12- SA19
IOR
IOW
SD0 - SD7
RESET
SLEEP
Pin #
36
37-48
49
50-54,58-60
61
62
65-68,71-74
75
77
The input pins not included in this test are:
Pin Name
AEN
TESTSEL
DI+
DI-
CI+
Pin #
63
76
79
80
81
Pin Name
CI-
RXD+
RXD-
XTAL1
Pin #
82
91
92
97
After the Input Cycle is complete, one more cy-
cle of AEN returns all digital output pins and
bi-directional pins to a high-impedance state.
Continuity Cycle
The combination of a complete Output Cycle, a
complete Input Cycle, and an additional AEN cy-
cle is called a Continuity Cycle. Each
Continuity Cycle lasts for 85 AEN clock cycles.
The first Continuity Cycle can be followed by
additional Continuity Cycles by keeping TEST-
SEL low and continuing to cycle AEN. When
TESTSEL is driven high, the CS8900 exits
Boundary Scan mode and AEN is again used as
the ISA-bus Address Enable.
Figure 6.1 shows a complete Boundary Scan
Continuity Cycle.
Figure 6.2 shows Boundary Scan timing.
DS150PP2
109
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