CS8900 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8900 Datasheet PDF : 132 Pages
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CS8900
Test Mode
AUI Internal
Loopback
AUI External
Loopback
AUI Collision
AUIloop
1
1
0
ENDECloop Description of Test
1
Transmit a frame and verify that the frame is received without error.
0
Connect DO+ to DI+ and D0- to DI-. Transmit a frame and verify that the
frame is received without error (since there is no collision signal, an SQE
error will occur).
0
Start transmission and observe DO+/DO- activity. Input a 10 MHz sine wave
to CI+/CI- pins and observe collisions.
Table 6.2. ADI Loopback and Collision Tests
6.1 Boundary Scan
Boundary Scan test mode provides an easy and
efficient board-level test for verifying that the
CS8900 has been installed properly. Boundary
Scan will check to see if the orientation of the
chip is correct, and if there are any open or short
circuits.
Boundary Scan is controlled by the TESTSEL
pin. When TESTSEL is high, the CS8900 is
configured for normal operation. When TEST-
SEL is low, the following occurs:
• the CS8900 enters Boundary Scan test mode
and stays in this mode as long as TESTSEL
is low;
• the CS8900 goes through an internal reset
and remains in internal reset as long as
TESTSEL is low;
• the AEN pin, normally the ISA bus Address
Enable, is redefined to become the Boundary
Scan shift clock input; and
• all digital outputs and bi-directional pins are
placed in a high-impedance state (this electri-
cally isolates the CS8900 digital outputs
from the rest of the circuit board).
Output Cycle, tests all digital output pins and all
bi-directional pins. The second cycle, known as
the Input Cycle, tests all digital input pins and all
bi-directional pins.
Output Cycle
During the Output Cycle, the falling edge of
AEN causes each of the 17 digital output pins
and each of the 17 bi-directional pins to be
driven low, one at a time. The cycle begins with
LINKLED and advances in order counterclock-
wise around the chip though all 34 pins. This test
is referred to as a "walking 0" test.
The following is a list of output pins and bi-di-
rectional pins that are tested during the Output
Cycle:
Pin Name
ELCS
EECS
EESK
EEDataOut
DMARQ2
DMARQ1
DMARQ0
CSOUT
SD08-SD15
INTRQ2
Pin #
2
3
4
5
11
13
15
17
27-24,21-18
30
Pin Name
INTRQ1
INTRQ0
IOCS16
MEMCS16
INTRQ3
IOCHRDY
SD0 - SD7
BSTATUS
LINKLED
LANLED
Pin #
31
32
33
34
35
64
65-68,71-74
78
99
100
For Boundary Scan to be enabled, AEN must be
low before TESTSEL is driven low.
A complete Boundary Scan test is made up of
two separate cycles. The first cycle, known as the
The output pins not included in this test are:
Pin Name
DO+
DO-
TXD+
Pin #
83
84
87
Pin Name
TXD-
RES
XTAL2
Pin #
88
93
98
108
DS150PP2
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