CS8900 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

may be read back from the TxCMD register

(Register 9).

2. The host must write the frame’s length to the

TxLength register (PacketPage base + 0146h).

3. The host must read the BusST register (Regis-

ter 18)

The information written to the TxCMD register

tells the CS8900 how to transmit the next frame.

The bits that must be programmed in the

TxCMD register are described in Table 5.16.

Register 9, TxCMD

Bit Bit Name

Operation

6 7 Tx Start

clear clear

Start preamble after 5 bytes have

been transferred to the CS8900.

clear set

Start preamble after 381 bytes

have been transferred to the

CS8900.

set clear

Start preamble after 1021 bytes

have been transferred to the

CS8900.

set set

Start preamble after entire frame

has been transferred to the

CS8900.

8

Force When set, the CS8900 discards

any frame data currently in the

transmit buffer.

9

Onecoll When set, the CS8900 will not

attempt to re-transmit any packet

after a collision.

C InhibitCRC When set, the CS8900 does not

append the 32-bit CRC value to the

end of any transmit packet.

D

TxPadDis When set, the CS8900 will not add

pad bits to short frames.

Table 5.16. Tx Command Configuration

For each individual packet transmission, the host

must issue a complete Transmit Request. Further-

more, the host must write to the TxCMD register

before each packet transmission, even if the con-

tents of the TxCMD register do not change. The

Transmit Request described above may be in

either Memory Space or I/O Space, as follows:

5.7.6 Transmit in Poll Mode

In poll mode, Rdy4TxiE bit (Register B

“BufCFG”, Bit 8) must be clear (Interrupt Dis-

abled). The transmit operation occurs in the

following order and is shown in Figure 5.12

1. The host bids for frame storage by writing the

Transmit Command to the TxCMD register

(memory base+ 0144h in memory mode and

I/O base + 0004h in I/O mode).

2. The host writes the transmit frame length to

the TxLength register (memory base + 0146h

in memory mode and I/O base + 0006h in I/O

mode). If the transmit length is erroneous, the

command is discarded and the TxBidErr bit

(Register 18, BusST, Bit 7) is set.

3. The host reads the BusST register. This read is

performed in memory mode by reading Regis-

ter 18, at memory base + 0138h. In I/O mode,

the host must first set the PacketPage Pointer

at the correct location by writing 0138h to the

PacketPage Pointer Port (I/O base + 000Ah).

The host can then read the BusST register

from the PacketPage Data Port (I/O base +

000Ch).

After reading the register, the Rdy4TxNOW

bit (Bit 8) is checked. If the bit is set, the

frame can be written. If the bit is clear, the

host must continue reading the BusST register

(Register 18) and checking the Rdy4TxNOW

bit (Bit 8) until the bit is set.

When the CS8900 is ready to accept the frame,

the host transfers the entire frame from host

memory to CS8900 memory using “REP” in-

struction (REP MOVS to memory base + 0A00h

in memory mode, and REP OUT to Re-

ceive/Transmit Data Port (I/O base + 0000h) in

I/O mode).

DS150PP2

101

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