AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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Watchdog Timer
Figure 42. Watchdog Timer
AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT)
that automatically resets the chip if it software fails to reset the WDT before the selected
time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc =
12MHz in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis-
ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST
register no instruction in between. When the Watchdog Timer is enabled, it will incre-
ment every machine cycle while the oscillator is running and there is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it
should be serviced in those sections of code that will periodically be executed within the
time required to prevent a WDT reset
Note: When the Watchdog is enable it is impossible to change its period.
RESET
WDTRST
Decoder
WR
Control
Fwd Clock
WDTPRG
Enable
14-bit COUNTER
7-bit COUNTER
Outputs
-
-
-
-
-
2
1
0
RESET
82 AT89C51CC03
4182K–CAN–05/06
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