Figure 47. CAN Controller Block Diagram
TxDC
RxDC
Bit
Timing
Logic
AT89C51CC03
Error
Counter
Rec/Tec
Bit
Stuffing /Destuffing
Cyclic
Redundancy Check
Receive Transmit
Page
Register
DPR(Mailbox + Registers)
Priority
Encoder
µC-Core Interface
Interface
Bus
Core
Control
CAN Controller Mailbox
and Registers
Organization
The pagination allows management of the 321 registers including 300(15x20) Bytes of
mailbox via 34 SFR’s.
All actions on the message object window SFRs apply to the corresponding message
object registers pointed by the message object number find in the Page message object
register (CANPAGE) as illustrate in Figure 48.
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4182K–CAN–05/06