AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT89C51CC03C-RLTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Registers

Table 103. ADCF Register

ADCF (S:F6h)

ADC Configuration

7

CH 7

6

CH 6

5

CH 5

4

CH 4

3

CH 3

Bit

Number

7-0

Bit

Mnemonic Description

CH 0:7

Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

Reset Value =0000 0000b

2

CH 2

1

CH 1

0

CH 0

Table 104. ADCON Register

ADCON (S:F3h)

ADC Control Register

7

6

5

4

3

2

1

0

-

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit

Bit

Number Mnemonic Description

7

-

Pseudo Idle Mode (Best Precision)

6

PSIDLE Set to put in idle mode during conversion

Clear to convert without idle mode.

Enable/Standby Mode

5

ADEN Set to enable ADC

Clear for Standby mode (power dissipation 1 uW).

End Of Conversion

4

ADEOC

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

Start and Status

3

ADSST Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0

SCH2:0

Selection of Channel to Convert

see Table 102

Reset Value =X000 0000b

158 AT89C51CC03

4182K–CAN–05/06

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