4182K–CAN–05/06
AT89C51CC03
Table 65. CANSTCH Register
CANSTCH (S:B2h)
CAN Message Object Status Register
7
DLCW
6
TXOK
5
RXOK
4
BERR
3
SERR
2
CERR
1
FERR
0
AERR
Bit
Number Bit Mnemonic Description
Data Length Code Warning
7
DLCW
The incoming message does not have the DLC expected. Whatever the frame
type, the DLC field of the CANCONCH register is updated by the received
DLC.
Transmit OK
The communication enabled by transmission is completed.
6
TXOK
When the controller is ready to send a frame, if two or more message objects
are enabled as producers, the lower index message object (0 to 13) is
supplied first.
This flag can generate an interrupt.
Receive OK
The communication enabled by reception is completed.
5
RXOK In the case of two or more message object reception hits, the lower index
message object (0 to 13) is updated first.
This flag can generate an interrupt.
Bit Error (Only in Transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
4
BERR the monitored recessive bit sent as a dominant bit during the arbitration field
and the acknowledge slot detecting a dominant bit during the sending of an
error frame.
This flag can generate an interrupt.
Stuff Error
3
SERR Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt.
CRC Error
The receiver performs a CRC check on each destuffed received message
2
CERR
from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a CRC error is
set.
This flag can generate an interrupt.
Form Error
The form error results from one or more violations of the fixed form in the
following bit fields:
1
FERR CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt.
Acknowledgment Error
0
AERR No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt.
Note: See Figure 50.
No default value after reset.
119