AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
| |||
AT89C51CC03
Table 60. CANBT1 Register
CANBT1 (S:B4h)
CAN Bit Timing Registers 1
7
6
5
4
3
2
1
0
-
BRP 5
BRP 4
BRP 3
BRP 2
BRP 1
BRP 0
-
Bit
Number Bit Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud rate prescaler
The period of the CAN controller system clock Tscl is programmable and
determines the individual bit timing.
6-1
BRP5:0
BRP[5..0] + 1
Tscl =
Fcan
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is dis-
abled with the ENA bit of the CANGCON register set to 0.
See Figure 52.
No default value after reset.
4182K–CAN–05/06
115
Share Link: 