AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT89C51CC03C-RLTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

AT89C51CC03

Table 62. CANBT3 Register

CANBT3 (S:B6h)

CAN Bit Timing Registers 3

7

6

5

4

3

2

1

0

-

PHS2 2

PHS2 1

PHS2 0

PHS1 2

PHS1 1

PHS1 0

SMP

Bit

Number Bit Mnemonic Description

7

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Phase Segment 2

This phase is used to compensate for phase edge errors. This segment can

be shortened by the re-synchronization jump width.

6-4

PHS2 2:0

Tphs2 = Tscl x (PHS2[2..0] + 1)

Phase segment 2 is the maximum of Phase segment 1 and the Information

Processing Time (= 2TQ).

Phase Segment 1

This phase is used to compensate for phase edge errors. This segment can

3-1

PHS1 2:0 be lengthened by the re-synchronization jump width.

Tphs1 = Tscl x (PHS1[2..0] + 1)

Sample Type

0 - once, at the sample point.

0

SMP

1 - three times, the threefold sampling of the bus is the sample point and twice

over a distance of a 1/2 period of the Tscl. The result corresponds to the

majority decision of the three values.

Note:

The CAN controller bit timing registers must be accessed only if the CAN controller is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 52.

No default value after reset.

4182K–CAN–05/06

117

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