CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

CLK

SYNC

Decimation

Engine

Clock Divider

and

MSYNC

Generator

CONFIG Register

Figure 50. Clock and MSYNC Generation

Internal

Clocks

MCLK

MSYNC

12. SYSTEM SYNCHRONIZATION

In many applications the CS5376 is used to create

a distributed measurement network. To be useful,

data sets from multiple sensors in a network must

have a known timing relationship between them.

Synchronous multi-sensor data can be combined

during post-processing to provide much more in-

formation than data from only a single sensor. To

establish a standardized timing relationship be-

tween sensors, the CS5376 can be synchronized

with the external network.

dog timer, sinc filter, and modulator are selected

from these generated clocks via the CONFIG reg-

ister (0x00).

When the input clock is synchronous to the external

network, the internal clocks of the CS5376 will

also be synchronous. A synchronous input clock

can only be guaranteed by careful design of clock

distribution in the external network. See “System

Design” on page 13 for more information about the

design requirements for a synchronous clock distri-

bution network.

12.1 Synchronous Clocking

The CS5376 uses an input clock of 32.768 MHz

and divides it down to generate internal clock fre-

quencies of 8.192 MHz, 4.096 MHz, 2.048 MHz,

1.024 MHz, 512 kHz, 256 kHz, 128 kHz, and 32

kHz. Clock rates for the decimation engine, watch-

12.2 Synchronization Signals

In addition to synchronous clocking, the signal

measurement and analysis functions should be

phase aligned. To accomplish this the CS5376 has

a synchronization input pin, SYNC, that phase

aligns the modulator clocks and digital filters.

SYNC - Device Synchronization Input Signal, pin 59

Input synchronization signal. MSYNC is generated from a rising edge on this pin to

synchronize the modulators, sinc filter, and decimation engine.

MSYNC - Modulator Sync Output, pin 14

A transition from logic low to high reinitializes the modulator timing to be synchronous

with the timing of the CS5376. Generated from the SYNC input signal.

Figure 51. Synchronization Pins

DS256PP1

77

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