CS5376 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376 Datasheet PDF : 122 Pages
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CS5376
occur during the transaction. The easiest way to
guarantee this is to gate the SDTKI input signal
with the SDRDY output signal using an AND gate.
When an SD port transaction is initiated, the
SDRDY signal is driven low by the CS5376 which
gates off the SDTKI input. When the SD port trans-
action is complete, the SDRDY signal automatical-
ly returns high to re-enable the SDTKI input.
Requested Output Configuration
When using the SD port in a requested output con-
figuration, a single pulse to the SDTKI pin initiates
an SD port transaction. The pulse is generated by a
controller that schedules the data into the commu-
nication network. Because data is requested only
when the controller is ready to receive, local data
buffering between the CS5376 and the communica-
tion network is not required.
Once the SD port transaction is completed, the
SDTKO output pin automatically generates a pulse
that can trigger the SDTKI pin of another CS5376.
In this way a pulse ‘token’ started by the communi-
cations controller can pass through a series of dai-
sy-chained CS5376 devices, initiating SD port
transactions in each. The final CS5376 SDTKO
output can be returned to the controller to signal the
end of a polling cycle.
10.4 SD Port Data Format
Each serial transaction is composed of a series of
32-bit words. The first 8 bits of each word are status
information containing an MFLAG indicator,
channel number bits, a time break flag, and a port
overflow flag. The last 24 bits of each output word
are the conversion data for the indicated channel.
The status and data sections of an output word are
shown in Figure 47.
MFLAG Indicator Bit - MFLAG
The MFLAG indicator is set whenever the
MFLAG signal is received from the modulators on
the MFLAG1-MFLAG4 pins. Each conversion
channel has an independent MFLAG input, and the
MFLAG indicator is independently set in the out-
put word for each channel.
31
23
0
Status
Data
MFLAG
--
31
30
Word 1
Status
Data
CH[1]
CH[0]
--
TB
29
28
27
26
00 - Channel 1
01 - Channel 2
10 - Channel 3
11 - Channel 4
Word 2
Word 3
128 bits
Figure 47. SD Port Output Words
--
W
25
24
Word 4
DS256PP1
73
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