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CS5376 View Datasheet(PDF) - Cirrus Logic

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Description
MFG CO.
CS5376 Datasheet PDF : 122 Pages
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CS5376
8.2 Hardware Sinc Filter
The hardware sinc filter provides high-order atten-
uation of out-of-band noise components from the
∆−Σ modulators. It also decimates the 512 kHz 1-
bit ∆−Σ data into lower frequency 24-bit data suit-
able for the FIR and IIR filters.
The hardware sinc filter is divided into two cascad-
ed sections, Sinc1 and Sinc2. Sinc1 is a fixed 5th
order decimate by 8 sinc filter while Sinc2 is a
multi-stage variable order sinc filter capable of
decimation ratios of 2, 4, 8, 12, or 16. The selected
output word rate and output filter stage from the
overall filter chain automatically determines the
decimation ratio selected for Sinc2.
Once the decimation ratio for Sinc2 is set, all en-
abled channels are decimated and filtered using an
identical hardware algorithm. The final output
from the sinc filter is 24-bit 2s complement data
that passes to the decimation engine for further fil-
tering by the FIR and IIR stages.
8.2.1 SINC1 Filter
The first part of the hardware sinc filter is Sinc1, a
fixed 5th order decimate by 8 sinc filter. This filter
decimates the incoming 512 kHz (or oversampled
256 kHz) 1-bit ∆−Σ bit stream from the modulators
down to a 64 kHz rate.
This filter section can be modeled as a 5th order
sinc filter with a decimate by 8 output. The time do-
main coefficients are [1, 5, 10, 10, 5, 1], and the fre-
quency domain model is [(sin x)/x]5.
8.2.2 SINC2 Filter
The second part of the hardware sinc filter is Sinc2,
a multi-stage, variable order, variable decimation
sinc filter. Depending on the selected output word
rate and output filter stage from the overall filter
chain, different cascaded Sinc2 stages are enabled.
See Figure 37 for a listing of possible Sinc2 config-
urations.
Stage 1 of Sinc2 can be modeled as a 4th order sinc
filter with a decimate by 2 output. The time domain
1-bit ∆−Σ,
512 kHz
5th order
sinc1
8
4th order
sinc2
stage1
2
4th order
sinc2
stage3
2
5th order
sinc2
stage4
2
6th order
sinc2
stage5
2
24-bit,
4 kHz -
32 kHz
4th order
sinc2
stage2
3
Figure 36. Sinc1 and Sinc2 Filter Stages
DS256PP1
58

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