CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

Modulator

Input

512 kHz

Sinc Filter

16-128

FIR1

4,16

FIR2

2,4

IIR1

1st Order

IIR2

2nd Order

DC Offset

& Gain

Correction

Output to High Speed Serial Data Port (SD Port)

Output Rate 62.5 Hz ~ 4 kHz

Figure 32. Digital Decimation Filter Stages

8. DIGITAL DECIMATION FILTER

The CS5376 digital filter consists of three sections:

a hardware sinc filter, two FIR filters, and a select-

able 1st, 2nd, or 3rd order IIR filter. The coeffi-

cients for the FIR and IIR filters are programmable

via the SPI 1 serial port, allowing the use of custom

filter sets optimized for specific applications. Ref-

erence coefficients are included in the CS5376

which are suitable for many applications.

Figure 32 illustrates the general flow of the filter

chain, along with the decimation ratios for each fil-

ter stage. The digital filters are structured to allow

data output following any stage in the filter chain.

If an application requires only a single FIR filter,

for example, conversion data can be taken immedi-

ately following the FIR1 filter stage.

The CS5376 digital filter supports output word

rates (OWRs) between 62.5 Hz and 4 kHz, though

not all output rates are supported for all output con-

figurations. The available decimation ratios limit

the FIR1 output configuration to output word rates

between 250 Hz and 4 kHz, while the sinc filter

output configuration supports only a 4 kHz output

word rate.

8.1 Filter Initialization

The CS5376 digital filters are initialized by setting

the decimation engine clock in the CONFIG regis-

ter (0x00), and then setting filter parameters in the

FILT_CFG register (0x20).

8.1.1 Decimation Engine Clock

The FIR and IIR filters are run in the decimation

engine, which is optimized for low-power digital

filter computations. The decimation engine clock

rate is programmable between 8.192 MHz and 32

kHz using the DFS bits (bits 16-18) in the CONFIG

register.

Computation Cycles

The appropriate decimation engine clock rate de-

pends on the computation cycles required to com-

plete the digital filters at the selected output word

rate. Lower clock rates consume less power but

cannot complete complex filters at high output

word rates.

Filter complexity is proportional to the total num-

ber of FIR filter coefficients and the selected order

of the IIR filter. Some experimentation will be re-

DS256PP1

53

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