CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

quired to determine the minimum clock rate that

can support a specified digital filter configuration.

Low-Power Standby Modes

A low-power standby mode exists to force the dec-

imation engine clock to 32 kHz, regardless of the

clock rate setting in the CONFIG register. This

mode is intended for battery powered systems that

idle for extended periods. The SBY bit (bit 2) in the

CONFIG register enables the decimation engine

low-power standby mode.

Standby mode slows the decimation engine clock,

but does not halt filter operation. To place the

CS5376 into a full sleep mode, the ‘Stop Filter’

command in the SPI 1 port should be issued to dis-

able the digital filters. The ‘Stop Filter’ command

halts the sinc filter and disables writes to the SD

port, placing these blocks into a low-power state.

After the filters are stopped, setting the SBY bit in

the CONFIG register minimizes power in the deci-

mation engine. While writing the SBY bit, clearing

the MCKEN and MCKEN2 bits disables the mod-

ulator clocks and places the modulators into a low-

power state.

To recover from sleep mode, write the CONFIG

register to clear the SBY bit and re-enable the mod-

ulator clocks, and then send the ‘Start Filter’ SPI 1

command. See “Serial Peripheral Interface 1” on

page 21 for a description of the ‘Stop Filter’, ‘Start

Filter’, and register write SPI 1 commands.

8.1.2 Channel Enable

The CS5376 can perform digital filtering for up to

four ∆−Σ modulators. The number of enabled chan-

nels is set by the CH bits (bits 0,1) in the

FILT_CFG register. The channels are enabled se-

quentially, with the one channel configuration us-

ing channel 1, the two channel configuration using

channels 1 and 2, the three channel configuration

using channels 1, 2, and 3, and the four channel

configuration using all four channels.

When fewer than four channels are required, the

number of decimation engine computation cycles

required to complete the digital filters is reduced

proportionally. This permits slower decimation en-

gine clock rates, and lower power consumption, for

reduced channel count applications.

8.1.3 Output Filter Selection

The CS5376 digital filters can output data follow-

ing any stage in the filter chain. The output filter

stage is selected using the FSEL bits (bits 8-10) in

the FILT_CFG register. Output data can be taken

from the sinc filter, the FIR1 filter, the FIR2 filter,

the 1st order IIR filter, the 2nd order IIR filter, or

the 3rd order IIR filter (by running both the 1st and

2nd order IIR filters).

When an output filter stage is selected, earlier filter

stages must be completed. For example, it is not

possible to run only the 1st order IIR filter without

first running the FIR1 and FIR2 filters. One excep-

tion is the 2nd order IIR filter which automatically

bypasses the 1st order IIR filter.

DS256PP1

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