CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

on the analog inputs. Once the overrange signal is

removed, the modulator recovers and the MFLAG

signal is cleared. The invalid data during the over-

range condition must propagate through the filter

chain, so the digital filters require time to recover

after an MFLAG error.

The MFLAG pin input value is included as an error

flag in the SD port status byte for that channel.

When an MFLAG signal is received from a modu-

lator, the error flag is output in the next status byte

without delay. Depending on the group delay of the

digital filters, a few words of valid data will be out-

put from the SD port before the invalid data propa-

gates through. See “Serial Data Output Port” on

page 71 for more information on the SD port status

byte and the MFLAG error bit.

7.4 Modulator Clock Generation

The MCLK and MCLK/2 outputs are low-jitter,

low-skew modulator clocks. The MCLK pin can

generate a 4.096 MHz, 2.048 MHz, 1.024 MHz, or

512 kHz clock from a 32.768 MHz master clock,

with the rate selected in the CONFIG register

(0x00). MCLK/2 always produces a clock at half

the selected MCLK rate. The CS5372 modulator

expects an MCLK rate of 2.048 MHz, while the

CS5321 expects an MCLK rate of 1.024 MHz.

7.4.1 Modulator Clock Enables

The MCKEN and MCKEN2 bits in the CONFIG

register independently enable the MCLK and

MCLK/2 outputs. At powerup or after RESET, the

MCLK and MCLK/2 pins are disabled and driven

low. When system configuration sets the MCKEN

or MCKEN2 bits, the internally-generated MCLK

MCLK - Modulator Clock Output, pin 13

Generated output clock to operate the CS5372 modulator. The clock frequency is

selectable, typically 2.048 MHz.

MCLK/2 - Modulator Clock Divided by 2 Output, pin 12

Generated output clock to operate the CS5321 modulator. The clock frequency is

selectable, typically 1.024 MHz.

MSYNC - Modulator Sync Output, pin 14

Generated output synchronization signal to reinitialize the modulator timing. Generated

from the SYNC input signal.

MDATA[4:1] - Modulator Data Input, pin 15, 17, 19, 21

Modulator data input, a one-bit serial data stream (one’s density) at a rate dictated by

the rate of the MCLK signal. 512 kbit and 256 kbit are typical MDATA rates.

MFLAG[4:1] - Modulator Flag Input, pin 16, 18, 20, 22

Logic input indicating the modulator is unstable due to an over-ranged signal on its

analog input.

Figure 29. Modulator Data Interface Pins

DS256PP1

50

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