CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

SYNC

MCLK

(2.048 MHz)

MSYNC

tmsd

tmsh

tmsd

MDATAx

(512 kHz)

Data1

Data2

Note: MDATA at 256 kHz has the same start timing, but takes 8 MCLK cycles to update.

tmsd = TMCLK / 4

tmsh = TMCLK

For fMCLK = 2.048 MHz:

tmsd = 122 ns

tmsh = 488 ns

Figure 30. SYNC and MSYNC Timing

or MCLK/2 signals begin driving their respective

pins starting from the next internal 32 kHz clock

synchronization boundary.

ment network. See “System Synchronization” on

page 77 for more information about how the

MSYNC signal is generated from the SYNC input.

7.5 Modulator Synchronization

The MSYNC output is generated from an external

input on the SYNC pin. MSYNC phase aligns the

sampling instant of the modulators and guarantees

synchronous analog sampling across a measure-

7.5.1 Modulator Sync Enable

Clearing the MSEN bit in the CONFIG register

(0x00) disables generation of the MSYNC signal,

the default state is for MSYNC generation to be en-

abled.

DS256PP1

51

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