CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

MCLK

MCLK/2

MSYNC

MDATA[4:1]

MFLAG[4:1]

MCLK /

MSYNC

Generate

MDI Input

512 kHz

CLK

SYNC

SINC

Filter

FIR

Filters

IIR

Filter

DC Offset

& Gain

Correction

Output to High Speed Serial Data Port (SD Port)

Output Rate 62.5 Hz ~ 4 kHz

Figure 28. Modulator Data Interface

7. MODULATOR DATA INTERFACE

The CS5376 provides digital filtering for up to four

∆−Σ modulators. The signals to and from the mod-

ulators are connected through the modulator data

interface (MDI).

7.1 Modulator Interface Pin Descriptions

Each modulator has a dedicated data input to an

MDATA pin, a dedicated error flag input to an

MFLAG pin, a shared modulator clock signal from

the MCLK pin, and a shared synchronization signal

from the MSYNC pin.

MCLK, MCLK/2 - Pins 13, 12

Generated output clocks for the modulators.

MSYNC - Pin 14

Generated output synchronization signal to reini-

tialize the modulator timing. Generated from the

SYNC input signal.

MDATA1 - MDATA4 - Pins 15, 17, 19, 21

Modulator data input, a one-bit serial data stream

(one’s density) at a rate dictated by the rate of the

MCLK signal. 512 kbit and 256 kbit are typical

MDATA rates.

MFLAG1 - MFLAG4 - Pins 16, 18, 20, 22

Logic input indicating the modulator is unstable

due to an over-ranged signal on its analog input.

7.2 Modulator Data Inputs

The MDATA inputs are expected to be 1-bit ∆−Σ

data at a 512 kHz or 256 kHz rate. The one’s den-

sity input is defined as full scale positive at 86%

and full scale negative at 14%, with overhang capa-

bility to 93% and 7%. Note that no signal input pro-

duces a 50% one’s density from the modulators.

The CS5372 modulator generates compatible data

at a 512 kHz rate, while the CS5321 modulator

generates compatible data at a 256 kHz rate. Both

data rates use an MDIFS setting of 512 kHz in the

CONFIG register (0x00) since the 256 kHz data

rate can be oversimple.

7.3 Modulator Flag Inputs

An MFLAG signal from a modulator indicates it

has become unstable due to an overrange condition

DS256PP1

49

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