CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

6.4 SPI 2 Transactions

The SPI 2 port operates as an SPI master to perform

write and read transactions with serial slave periph-

erals. The exact timing of the SPI transactions de-

pends on the SPI mode, selected using the SCKPO

and SCKPH bits in the SPI2CTRL register.

Write Transactions

Write transactions are initialized by writing an SPI

‘write’ (0x02) opcode and an 8-bit destination ad-

dress to the SPI2CMD register, and the output data

value to the SPI2DAT register. Writing the

D2SREQ bit in the SPI2CTRL register starts the

SPI 2 transaction based on the SPI2CTRL configu-

ration.

A write transaction outputs 1 or 2 bytes from the

SPI2CMD register and 0, 1, 2, or 3 bytes from the

SPI2DAT register. Write transactions are therefore

a minimum of 1 byte (DNUM = 0) and a maximum

of 5 bytes (DNUM = 4). The SPI 2 port uses the

DNUM bits in the SPI2CTRL register to determine

the total number of bytes to send during a write

transaction.

Write transactions are not required to use standard

SPI commands. If serial peripherals use non-stan-

dard write commands they can be written to the

SPI2CMD and SPI2DAT registers as required.

Read Transactions

Read transactions are initialized by writing an SPI

‘read’ (0x03) opcode and an 8-bit source address to

the SPI2CMD register. Writing the D2SREQ bit in

the SPI2CTRL register starts the SPI 2 transaction

based on the SPI2CTRL configuration, with the in-

put data value received to the SPI2DAT register.

A read transaction outputs 2 bytes from the

SPI2CMD register and can receive 1, 2, or 3 bytes

into the SPI2DAT register. Read transactions are a

minimum of 3 bytes (DNUM = 2) and a maximum

of 5 bytes (DNUM = 4). The SPI 2 port uses the

DNUM bits in the SPI2CTRL register to determine

the total number of bytes to send and receive during

a read transaction.

Read transactions are not required to use standard

SPI commands. If a serial peripherals use non-stan-

dard read commands they can be written to the

SPI2CMD register, as long as they conform to the

format of 2 bytes out with 1, 2, or 3 bytes in.

SPI Modes

The SPI mode for the SPI 2 port is selected in the

SPI2CTRL register using the SCKPO and SCKPH

bits. Supported modes are:

SPI Mode 0 (0,0): SCKPO = 0, SCKPH = 0

SPI Mode 1 (0,1): SCKPO = 0, SCKPH = 1

SPI Mode 2 (1,0): SCKPO = 1, SCKPH = 0

SPI Mode 3 (1,1): SCKPO = 1, SCKPH = 1

The most commonly used SPI modes are mode 0

and mode 3, both of which define the serial clock

with data valid on rising edges and transitioning on

falling edges.

In SPI mode 0, the SCK2 serial clock is defined ini-

tially in a low state. Output data on the SO pin is

valid immediately after the chip select pin goes

low, and the first rising edge of SCK2 latches valid

data.

In SPI mode 3, the SCK2 serial clock is defined ini-

tially in a high state. Output data on the SO pin is

invalid until the initial falling edge of SCK2, and

the first rising edge of SCK2 latches valid data.

SPI modes 1 and 4 work similarly to modes 0 and

3, with the serial clock defined to have data valid on

falling edges and transitioning on rising edges.

DS256PP1

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