CS5376 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376 Datasheet PDF : 122 Pages
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6.3.4 SPI2CTRL Register
CS5376
Figure 23. SPI 2 Configuration Register SPI2CTRL
(MSB) 23
WOM
R/W
0
22
SCKFS2
R/W
0
21
SCKFS1
R/W
1
20
SCKFS0
R/W
1
19
SPI2EN4
R/W
0
18
SPI2EN3
R/W
0
17
SPI2EN2
R/W
0
16
SPI2EN1
R/W
0
15
RCH1
R/W
0
14
RCH0
R/W
0
13
D2SOP
R
0
12
SCKPH
R/W
0
11
SWEF
R/W
0
10
SCKPO
R/W
0
9
8
TM
D2SREQ
R/W
R/W
0
0
7
6
5
4
3
2
1
(LSB) 0
DNUM2
DNUM1
DNUM0
CS4
CS3
CS2
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
0
0
0
0
I/O Address: 0x10
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable
and Writable
Bits in bottom rows
are reset condition.
Bit definitions:
23 WOM
22:20 SCKFS
[2:0]
19:16 SPI2EN
[4:1]
Wired-OR Mode
15:14 RCH SPI2 Read Channel 7:5
1: Enabled (open drain)
[1:0]
11: Channel 4
0: Disabled (push-pull)
10: Channel 3
01: Channel 2
00: Channel 1
SCK2 Frequency
111: reserved
110: reserved
101: 4.096 MHz
100: 2.048 MHz
011: 1.024 MHz
010: 512 kHz
001: 128 kHz
000: 32 kHz
13 D2SOP DE to SPI2 Operation in 4
Progress
12 SCKPH SCK2 Phase
3
1: Data out at first SCK2
edge
2
0: Data out before first
SCK2 edge
11 SWEF SPI2 Write Collision 1
Error Flag
SPI2 Channel Enable 10 SCKPO SCK2 Polarity
0
1: Enabled
1: On falling edge
0: Disabled (default)
0: On rising edge
9 TM
SPI2 Timeout
1: SPI2 timed out
0: not timed out
8 D2SREQ DE to SPI2 Request
1: Request operation
0: Operation done
(cleared by SPI2)
DNUM
[2:0]
Decimation Engine
Number of bytes in
transaction (1-8)
CS4
Chip Select 4 Enable
CS3
Chip Select 3 Enable
CS2
Chip Select 2 Enable
CS1
Chip Select 1 Enable
CS0
Chip Select 0 Enable
DS256PP1
43
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