CS5376 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376 Datasheet PDF : 122 Pages
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CS5376
During a transaction the data in the SPI2DAT reg-
ister is written or read after the command and ad-
dress bytes from the SPI2CMD register are written.
6.3.3 SPI 2 Configuration Register
The SPI 2 port is configured using the SPI2CTRL
register (0x10) in the decimation engine. Bits in
this register select the serial input pin and chip se-
lect pin used for a transaction, set the total number
of bytes in a transaction, initiate a transaction using
the D2SREQ bit, and report status and error infor-
mation about a transaction. Other bits in the
SPI2CTRL register set general port configuration
options such as the serial clock rate, the SPI mode,
and the state of the internal pull-up resistors.
Serial Input Configuration
The serial input pin used to receive data is selected
using the SPI2EN bits (bits 19 - 16) and the RCH
bits (bits 14, 15). The SPI2EN bits enable the in-
puts, while the RCH bits select the specific channel
for the SPI 2 transaction.
Chip Select Configuration
The chip select pin used during a transaction is se-
lected using the CS0, CS1, CS2, CS3, and CS4 bits
(bits 0 - 4). Multiple chip selects can be enabled to
send a transaction to more than one serial peripher-
al, if required.
Number of Transaction Bytes
The DNUM bits (bits 5 - 7) are used to specify the
total number of bytes to be transferred during a
transaction. DNUM is zero based and represents
one greater than the number programmed, i.e.
DNUM = 3 specifies a 4 byte transaction.
Initiating SPI 2 Transactions
Writing to the D2SREQ bit (bit 8) starts an SPI 2
transaction. When the transaction is completed, the
D2SREQ bit is automatically cleared.
Status and Error Information
Three bits in the SPI2CTRL register are used to re-
port status and error information.
The D2SOP flag is set when the SPI 2 port is busy
performing a transaction. It is automatically
cleared when the transaction is completed.
The SWEF flag is set if a request to initiate a new
transaction occurs during the current transaction.
This flag is latched and must be cleared manually.
The TM flag indicates the SPI 2 port timed out on
the requested transaction. This flag is latched and
must be cleared manually.
Serial Clock Rate
The output serial clock rate on the SCK2 pin is set
by the SCKFS bits (bits 20 - 22). The clock rate can
be set between 32 kHz and 4.096 MHz.
SPI Mode
The serial mode used for a transaction depends on
the SCKPO and SCKPH bits (bits 10 and 12 re-
spectively). The SPI 2 port supports all SPI modes,
with mode 0 and mode 3 the most commonly used.
SPI Mode 0 (0,0) uses SCKPO = 0 and SCKPH =
0, with SPI mode 3 (1,1) using SCKPO = 1 and
SCKPH = 1.
Internal Pull-Up Resistors
The SPI 2 pins have internal pull-up resistors that
are disabled by setting the WOM bit (bit 23). The
WOM bit enables ‘wired-or’ mode which permits
multiple serial devices to connect together without
the extra power drain of an internal pull-up resistor.
DS256PP1
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