
5.3.3 SPI1CMD Register
CS5376
Figure 16. SPI 1 Command Register SPI1CMD
(MSB) 23
S1CMD23
R/W
0
22
S1CMD22
R/W
0
21
S1CMD21
R/W
0
20
S1CMD20
R/W
0
19
S1CMD19
R/W
0
18
S1CMD18
R/W
0
17
S1CMD17
R/W
0
16
S1CMD16
R/W
0
15
S1CMD15
R/W
0
14
S1CMD14
R/W
0
13
S1CMD13
R/W
0
12
S1CMD12
R/W
0
11
S1CMD11
R/W
0
10
S1CMD10
R/W
0
9
S1CMD9
R/W
0
8
S1CMD8
R/W
0
7
S1CMD7
R/W
0
6
S1CMD6
R/W
0
5
S1CMD5
R/W
0
4
S1CMD4
R/W
0
3
S1CMD3
R/W
0
2
S1CMD2
R/W
0
1
S1CMD1
R/W
0
(LSB) 0
S1CMD0
R/W
0
SPI 1 Address: 0x03
0x04
0x05
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 S1CMD[23:16] SPI 1 Command
High Byte
15:8 S1CMD[15:8] SPI 1 Command
Middle Byte
15:8 S1CMD[7:0] SPI 1 Command Low
Byte
DS256PP1
29