CS5376-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376-BS Datasheet PDF : 122 Pages
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5.3.2 SPI1CTRL Register
CS5376
(MSB) 23
--
R/W1
0
Figure 15. SPI Control Register SPI1CTRL
22
--
R/W1
0
21
SCK1PO
R/W
0
20
SCK1PH
R/W
0
19
WOM
R/W
1
18
SCK1FS2
R/W
0
17
SCK1FS1
R/W
1
16
SCK1FS0
R/W
1
15
SMODF
R
0
14
PROM
R/W
0
13
DEOP
R
0
12
EMOP
R
0
11
SWEF
R
0
10
SINT
R/W
0
9
8
IEN
E2DREQ
R/W
R/W
0
0
7
6
5
4
3
2
1
(LSB) 0
DNUM2
DNUM1
DNUM0
CS11
CS10
CS9
CS8
D2SREQ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
0
0
SPI 1 Address: 0x00
0x01
0x02
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:22 --
reserved
15
21 SCK1PO SCK1 polarity
14
1: On falling edge
0: On rising edge
20 SCK1PH SCK1 phase
13
1: Data out at first SCK1
edge
0: Data out before first
SCK1 edge
19 WOM Wired-OR logic
12
1: Enabled (open drain)
0: Disabled (push-pull)
18:16 SCK1FS SCK1 output freq.
11
[2:0]
111: reserved
110: reserved
10
101: 4.096 MHz
100: 2.048 MHz
011: 1.024 MHz
(default)
9
010: 512 kHz
001: 256 kHz
000: 32 kHz
8
SMODF SPI 1 mode fault error 7:5
PROM
DEOP
PROM mode
4
1: 2-byte address
0: 1-byte address
DE to SPI 1 operation in 3
progress
DNUM
[2:0]
CS11
DE number of bytes in
transaction (1-8 or 2-9)
SPI 1 chip select 11
CS10 SPI 1 chip select 10
EMOP External master to SPI 1 2
operation in progress
SWEF SPI 1 write collision 1
error flag
SINT Serial Interrupt
0
IEN
SPI 1 Interrupt enable
E2DREQ External master to DE
request
CS9
SPI 1 chip select 9
CS8
SPI 1 chip select 8
D2SREQ DE to SPI request
1: Request operation
0: Operation done
(cleared by SPI)
DS256PP1
28
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