DSPIC33FJ32GS610-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

MFG CO.

DSPIC33FJ32GS610-I/PF

16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

Microchip Technology 

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

6.2 Power-on Reset (POR)

A Power-on Reset (POR) circuit ensures the device is

reset from power-on. The POR circuit is active until

VDD crosses the VPOR threshold and the delay, TPOR,

has elapsed. The delay, TPOR, ensures the internal

device bias circuits become stable.

The device supply voltage characteristics must meet

the specified starting voltage and rise rate

requirements to generate the POR. Refer to

Section 27.0 “Electrical Characteristics” for details.

The Power-on Reset (POR) status bit in the Reset

Control (RCON<0>) register is set to indicate the

Power-on Reset.

6.3 Brown-out Reset (BOR) and

Power-up Timer (PWRT)

The on-chip regulator has a Brown-out Reset (BOR)

circuit that resets the device when the VDD is too low

(VDD < VBOR) for proper device operation. The BOR

circuit keeps the device in Reset until VDD crosses the

FIGURE 6-3:

BROWN-OUT SITUATIONS

VDD

SYSRST

VBOR threshold and the delay, TBOR, has elapsed. The

delay, TBOR, ensures the voltage regulator output

becomes stable.

The Brown-out Reset (BOR) status bit in the Reset

Control (RCON<1>) register is set to indicate the

Brown-out Reset.

The device will not run at full speed after a BOR as the

VDD should rise to acceptable levels for full-speed

operation. The PWRT provides power-up time delay

(TPWRT) to ensure that the system power supplies have

stabilized at the appropriate levels for full-speed

operation before the SYSRST is released.

The Power-up Timer delay (TPWRT) is programmed by

the Power-on Reset Timer Value Select

(FPWRT<2:0>) bits in the FPOR Configuration

(FPOR<2:0>) register, which provides eight settings

(from 0 ms to 128 ms). Refer to Section 24.0 “Special

Features” for further details.

Figure 6-3 shows the typical brown-out scenarios. The

Reset delay (TBOR + TPWRT) is initiated each time VDD

rises above the VBOR trip point

TBOR + TPWRT

VBOR

VDD

SYSRST

VDD

VDD Dips Before PWRT Expires

SYSRST

TBOR + TPWRT

TBOR + TPWRT

VBOR

VBOR

 2009-2012 Microchip Technology Inc.

DS70591E-page 119

Share Link: