DSPIC33FJ32GS610-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

MFG CO.

DSPIC33FJ32GS610-I/PF

16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

Microchip Technology 

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

6.9 Using the RCON Status Bits

The user application can read the Reset Control

(RCON) register after any device Reset to determine

the cause of the Reset.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

Table 6-2 provides a summary of the Reset flag bit

operation.

TABLE 6-2: RESET FLAG BIT OPERATION

Flag Bit

Set by:

TRAPR (RCON<15>)

IOPWR (RCON<14>)

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

Trap conflict event

Illegal opcode or uninitialized W register

access or Security Reset

MCLR Reset

RESET instruction

WDT time-out

SLEEP (RCON<3>) PWRSAV #SLEEP instruction

IDLE (RCON<2>)

PWRSAV #IDLE instruction

BOR (RCON<1>)

POR, BOR

POR (RCON<0>)

POR

Note: All Reset flag bits can be set or cleared by user software.

POR, BOR

POR, BOR

Cleared by:

POR

POR, BOR

PWRSAV instruction, CLRWDT instruction,

POR, BOR

POR, BOR

POR, BOR

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 2009-2012 Microchip Technology Inc.

DS70591E-page 121

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