DSPIC33FJ32GS610-I/PF View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
DSPIC33FJ32GS610-I/PF
Microchip Technology
DSPIC33FJ32GS610-I/PF Datasheet PDF : 456 Pages
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
bit 15
U-0
—
bit 7
R/W-0(1)
U-0
ERASE
—
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
—
NVMOP<3:0>(2)
U-0
—
bit 8
R/W-0(1)
bit 0
Legend:
R = Readable bit
-n = Value at POR
SO = Settable Only bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit(1)
1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command
0 = Performs the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(1,2)
If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erases General Segment
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erases a single Configuration register byte
If ERASE = 0:
1111 = No operation
1101 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Programs a single Configuration register byte
Note 1: These bits can only be reset on a Power-on Reset.
2: All other combinations of NVMOP<3:0> are unimplemented.
2009-2012 Microchip Technology Inc.
DS70591E-page 111
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