CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

Address

0x8000.0780

Name

UMSEOI

0x8000.07C0

0x8000.0800

0x8000.0840

0x8000.0880–

0x8000.0FFF

0x8000.1000

0x8000.1100

0x8000.1140

0x8000.1240

0x8000.1280

0x8000.12C0–

0x8000.147F

0x8000.1480

0x8000.14C0

0x8000.1500

0x8000.1600

0x8000.16C0

0x8000.1700

0x8000.1800

COEOI

HALT

STDBY

Reserved

FBADDR

SYSCON2

SYSFLG2

INTSR2

INTMR2

Reserved

UARTDR2

UBLCR2

SS2DR

SRXEOF

SS2POP

KBDEOI

Reserved

0x8000.1840–

0x8000.1FFF

0x8000.2000

0x8000.2040

0x8000.2080

0x8000.20C0

0x8000.2100

0x8000.2200

0x8000.2240

0x8000.2280

0x8000.22C0

Reserved

DAIR

DAIR0

DAIDR1

DAIDR2

DAISR

SYSCON3

INTSR3

INTMR3

LEDFLSH

Default

—

—

—

—

RD/WR Size

Comments

WR — Write to clear UART modem status changed inter-

rupt.

WR — Write to clear CODEC sound interrupt.

WR — Write to enter the Idle State.

WR — Write to enter the Standby State.

Write will have no effect, read is undefined.

0xC

RW 4 LCD frame buffer start address.

0

RW 16 System control register 2.

0

RD 24 System status register 2.

0

RD 16 Interrupt status register 2.

0

RW 16 Interrupt mask register 2.

Write will have no effect, read is undefined. .

0

RW 16 UART2 Data register.

0

RW 32 UART2 bit rate and line control register.

0

RW 16 Master / slave SSI2 data register.

—

WR — Write to clear RX FIFO overflow flag.

—

WR — Write to pop SSI2 residual byte into RX FIFO.

—

WR — Write to clear keyboard interrupt.

—

WR — Do not write to this location. A write will cause the

processor to go into an unsupported power state.

—

Write will have no effect, read is undefined.

0

RW 32 DAI control register.

0

RW 32 DAI data register 0.

0

RW 32 DAI data register 1.

0

WR 21 DAI data register 2.

0

RW 32 DAI status register.

0

RW 16 System control register 3.

0

RD 32 Interrupt status register 3.

0

RW 8 Interrupt mask register 3.

0

RW 7 LED Flash register.

Table 31. CS89712 Internal Registers (Little Endian Mode) (Continued)

Big Endian Mode

0x8000.0003

Name

PADR

Default

0

RD/WR

RW

Size

Comments

8 Port A Data register

Table 32. CS89712 Internal Registers (Big Endian Mode)

70

DS502PP2

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