CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

1) Software bids for frame storage by writing the

Transmit Command to the TxCMD register.

2) Software writes the transmit frame length to the

TxLength register. If the transmit length is er-

roneous, the command is discarded and the Tx-

BidErr bit (BusST register bit 7) is set.

3) The BusST register is read. The software must

first set the Ethernet Port Pointer at the correct

location by writing 0138h to the Ethernet Port

Pointer Port. Software can then read the BusST

register from the Ethernet Port Data Port.

4) After the read, Rdy4TxNOW (bit 8) is checked.

If set, the frame can be written. If clear, the soft-

ware must continue reading the BusST register

and checking Rdy4TxNOW until set.

When the CS89712 is ready to accept the frame,

software transfers the frame from host RAM to

Ethernet port memory Receive/Transmit Data Port.

2.34.7 Transmit in Interrupt Mode

In interrupt mode, Rdy4TxiE bit (BufCFG register

bit 8) must be set for transmit operation. Transmit

operation occurs in the following order:

1) The software bids for frame storage by writing

the Transmit Command to the TxCMD register.

2) The software writes the transmit frame length

to the TxLength register. If the transmit length

is erroneous, the command is discarded and the

TxBidErr, bit 7, in BusST register is set.

3) The BusST register is read. If the Rdy4TxNOW

bit is set, the frame can be written to Ethernet

port memory. If Rdy4TxNOW is clear, soft-

ware will have to wait for the Ethernet port

buffer memory to become available at which

time an interrupt is generated. On interrupt, the

interrupt service routine reads ISQ register and

checks the Rdy4Tx bit (bit 8). If Rdy4Tx is

clear then the software waits for the next inter-

rupt. If Rdy4Tx is set, then the Ethernet port is

ready to accept the frame.

4) When the Ethernet port is ready to accept the

frame, the software transfers the entire frame

from host memory to Ethernet port memory to

Receive/Transmit Data Port.

2.34.8 Completing Transmission

When the CS89712 successfully completes trans-

mitting a frame, it sets the TxOK bit (TxEvent reg-

ister bit 8). If the TxOKiE bit (TxCFG register bit

8) is set, an interrupt is generated.

2.34.9 Rdy4TxNOW vs. Rdy4Tx

The Rdy4TxNOW bit (BusST register bit 8) is used

to indicate the Ethernet port is ready to accept a

frame for transmission. This bit is used during the

Transmit Request process or after the Transmit Re-

quest process to signal the software that space has

become available when interrupts are not being

used (i.e. Rdy4TxiE, bit 8 of Register B, is not set).

Also, the Rdy4Tx bit is used with interrupts and re-

quires the Rdy4TxiE bit be set.

2.34.10 Committing Buffer Space to a Frame

When the software issues a transmit request, the

Ethernet port checks the length of the transmit

frame to see if there is sufficient on-chip buffer

space. If there is, the Ethernet port sets the

Rdy4TxNOW bit. If not, and the Rdy4TxiE bit is

set, the Ethernet port waits for buffer space to free

up and then sets the Rdy4Tx bit.

Even though transmit buffer space may be avail-

able, the Ethernet port does not commit buffer

space to a transmit frame until all of the following

are true:

1) The software must issues a Transmit Request;

2) The Transmit Request must be successful; and,

3) Either the software reads that the Rdy4TxNOW

bit (BusST register bit 8) is set, or the software

reads that the Rdy4Tx bit (BufEvent register bit

8) is set.

DS502PP2

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