CS89712
Address
0x8000.0000
0x8000.0001
0x8000.0002
0x8000.0003
0x8000.0040
0x8000.0041
0x8000.0042
0x8000.0043
0x8000.0080
0x8000.00C0
0x8000.0100
0x8000.0140
0x8000.0180
0x8000.01C0
0x8000.0200
0x8000.0240
0x8000.0280
0x8000.02C0
0x8000.0300
0x8000.0340
0x8000.0380
0x8000.03C0
0x8000.0400
0x8000.0440
0x8000.0480
0x8000.04C0
0x8000.0500
0x8000.0540
0x8000.0580
0x8000.05C0
0x8000.0600
0x8000.0640
0x8000.0680
0x8000.06C0
0x8000.0700
0x8000.0740
Name
PADR
PBDR
—
PDDR
PADDR
PBDDR
—
PDDDR
PEDR
PEDDR
SYSCON1
SYSFLG1
MEMCFG1
MEMCFG2
INTSR1
INTMR1
LCDCON
TC1D
TC2D
RTCDR
RTCMR
PMPCON
CODR
UARTDR1
UBLCR1
SYNCIO
PALLSW
PALMSW
STFCLR
BLEOI
MCEOI
TEOI
TC1EOI
TC2EOI
RTCEOI
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
0
0
0
0
0
0
0
—
—
—
—
—
—
—
RD/WR Size
Comments
RW 8 Port A data register.
RW 8 Port B data register.
—
8 Reserved.
RW 8 Port D data register.
RW 8 Port A data direction register.
RW 8 Port B data direction register.
—
8 Reserved.
RW 8 Port D data direction register.
RW 3 Port E data register.
RW 3 Port E data direction register.
RW 32 System control register 1.
RD 32 System status flags register 1.
RW 32 Expansion memory configuration register 1.
RW 32 Expansion memory configuration register 2.
RW 32 Reserved.
RD 32 Interrupt status register 1.
RW 32 Interrupt mask register 1.
RW 32 LCD control register.
RW 16 Read / Write register sets and reads data to TC1.
RW 16 Read / Write register sets and reads data to TC2.
RW 32 Real Time Clock data register.
RW 32 Real Time Clock match register.
RW 12 PWM pump control register.
RW 8 CODEC data I/O register.
RW 16 UART1 FIFO data register.
RW 32 UART1 bit rate and line control register.
RW 32 Synchronous serial I/O data register for master
only SSI.
RW 32 Least significant 32-bit word of LCD palette register.
RW 32 Most significant 32-bit word of LCD palette register.
WR — Write to clear all start up reason flags.
WR — Write to clear battery low interrupt.
WR — Write to clear media changed interrupt.
WR — Write to clear tick and watchdog interrupt.
WR — Write to clear TC1 interrupt.
WR — Write to clear TC2 interrupt.
WR — Write to clear RTC match interrupt.
Table 31. CS89712 Internal Registers (Little Endian Mode)
DS502PP2
69