CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

Function

IrDA and

RS232

Interfaces

LCD

Keyboard and

Buzzer drive

LED Flasher

General

Purpose I/O

PWM

Drives

Boundary

Scan

Test

Signal

Name

LEDDRV

PHDIN

TXD[1-2]

RXD[1-2]

DSR

DCD

CTS

DD[0-3]

CL[1]

CL[2]

FRM

M

COL[0-7]

BUZ

PD[0]/

LEDFLSH

PA[0:7]

PB[0]/PRDY1

PB[1]/PRDY2

PB[2:7]

PD[0:7]

PE[0]/

BOOTSEL[0]

PE[1]/

BOOTSEL[1]

PE[2]

DRIVE[0:1]

FB[0:1]

TDI

TDO

TMS

TCLK

nTRST

nTEST[0:1]

Signal

Description

J7

O Infrared LED drive output (UART1)

K4

I Photo diode input (UART1)

L4, G5 O RS232 UART1 and 2 TX outputs

M4, H3 I RS232 UART1 and 2 RX inputs

M2

I RS232 DSR input

N1

I RS232 DCD input

L3

I RS232 CTS input

D3, C3, I/O LCD serial display data; pins can be used on power up to read

B3, A3

the ID of some LCD modules (See Figure 31).

C4

O LCD line clock

E5

O LCD pixel clock

D4

O LCD frame synchronization pulse output

E4

O LCD AC bias drive

O Keyboard column drives (SYSCON1)

R8

O Buzzer drive output (SYSCON1)

R4

O LED flasher driver — multiplexed with Port D bit 0. This pin can pro-

vide up to 4 mA of drive current.

I/O Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY

input); also used as keyboard row inputs

I/O Port B I/O. All eight Port B bits can be used as GPIOs.

When the PC CARD1 or 2 control bits in the SYSCON2 register are

de-asserted, PB[0] and PB[1] are available for GPIO. When

asserted, these port bits are used as the PRDY signals for connected

CL-PS6700 PC Card Host Adapter devices.

I/O Port D I/O

L5

I/O Port E I/O (3 bits only). Can be used as general purpose I/O during

normal operation.

M5

I/O During power-on reset, PE[0] and PE[1] are inputs and are latched by

the rising edge of nPOR to select the memory width that the CS89712

will use to read from the boot code storage device (i.e., external 8-bit-

wide FLASH bank).

J8

I/O During power-on reset, PE[2] is latched by the rising edge of nPOR to

enable the PLL clocking mode.

L9, L7

I/O PWM drive outputs. These pins are inputs on power up to determine

what polarity the output of the PWM should be when active. Other-

wise, these pins are always an output (See Table 91).

M9, P7 I PWM feedback inputs

G4

I JTAG data in

J4

O JTAG data out

T2

I JTAG mode select

T8

I JTAG clock

M15

I JTAG async reset

K6, J9

I Test mode select inputs are used in conjunction with the power-on

latched state of nURESET to select the various device test modes.

Table 90. External Signal Functions (Continued)

DS502PP2

143

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