CS61318-IP View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS61318-IP Datasheet PDF : 28 Pages
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CS61318
An address/command byte, shown in Figure 9,
points to addresses 0x10 through 0x14 (address
0x10 shown), and precedes a data byte. The first bit
of the address/command byte determines whether a
read or a write is requested. The next six bits con-
tain the address. The last bit is ignored. Data to the
internal registers is input on the eight clock cycles
immediately following the address/command byte.
CS
SCLK
SDI
SDO
CLKE = 0
R/W 0 0 0 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7
Address/Command Byte
Data Input/Output
D0 D1 D2 D3 D4 D5 D6 D7
Figure 9. Input/Output Timing (showing address 0x10)
Control Register 1
Control Register 2
Equalizer Gain
(EQGAIN)
Arbitrary Waveform RAM
Address
Reserved
Set to “0”
7
TAOS
AIS
X
MSB
0
6
5
4
3
LLOOP
RLOOP
Reserved
Set to “0”
Reserved
Set to “0”
RAMPLSE
Reserved
set to ‘0”
LOOPDN
LOOPUP
X
X
EQ4
EQ3
-
-
-
-
0
0
0
0
2
HDB3
RPWDN
EQ2
-
0
1
0
ADDR
NLOOP LOS 0x10 R/W
TxHIZ
Reserved
set to ‘0”
0x11 R/W
EQ1
EQ0 0x12 R
-
LSB 0x13 R/W
0
0
0x14
Note: All Control Registers initialize to 0x00.
Table 2. Register Map
12
DS441PP2
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