STLC2500
Figure 6. Linear mode
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
01
15
125 µs
Figure 7. Multi-slot operation
01
15
PCM_CLK
PCM_SYNC
P_SYNC_DELAY
PCM_A
PCM_B
DATA SIZE
125 µs
The PCM implementation supports from 1 up to 3 slots per frame with the following parameters:
Table 21. PCM interface parameters
Symbol
Description
PCM Interface
FPCM_CLK Frequency of PCM_CLK
FPCM_SYNC Frequency of PCM_SYNC
Psync_delay Delay of the starting of the first slot
Pclk_number Available PCM_CLK clock cycles
Ss
Slot starts (programmable for every slot)
D
Data size
N
Number of slots per frame
Min. Typ. Max. Unit
140
4000 kHz
8
kHz
0
255 cycles
0
255 cycles
0
255 cycles
8
16
bit
1
3
18/23