STLC2500 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STLC2500

BLUETOOTH™ SINGLE CHIP

STMicroelectronics 

STLC2500

Table 16. Receiver Parameters (Tamb = 25°C, VDD_HV = 2.75V, parameters are given at device pin.)

Symbol

C/I+3MHz

Parameter

Adjacent (+3MHz) interference

C/I-3MHz Adjacent (-3MHz) interference

C/I≥4MHz Adjacent (≥±4MHz) interference

Receiver inter-modulation

IMD

Inter-modulation

Test Condition

@ Input signal

strength = -67dBm

@ Input signal

strength = -67dBm

@ Input signal

strength = -67dBm

Measured as defined in BT

test specification.

Min. Typ. Max. Unit

-44

dB

-37

dB

-46

dB

-35

dBm

7.2 Transmitter

All output power specifications are given at the pin level and over temperature range unless otherwise

specified.

Table 17. Transmitter Parameters (Tamb = 25°C, VDD_HV = 2.75V, parameters are given at device pin.)

Symbol

Parameter

Test Condition

RFout Output frequency range

TXpout Nominal Output power

@2402-2480 MHz

In-band spurious emission

FCC

FCC’s 20 dB BW

TX_SE2 Channel offset=2

TX_SE3 Channel offset=3

TX_SE4 Channel offset≥4 (except 13)

Initial carrier frequency tolerance (for an exact reference)

∆F

|f_TX-f0|

Carrier Frequency Drift

|∆f_p1| One slot packet

|∆f_p3| Three slots packet

|∆f_p5| Five slots packet

Carrier Frequency Drift rate

|∆f/50us| Frequency drift rate

Min.

2402

0

Typ.

3

Max.

2480

5

Unit

MHz

dBm

932

kHz

-51

dBm

-55

dBm

-57

dBm

-75

75

kHz

25

kHz

40

kHz

40

kHz

20 kHz/µs

7.3 System clock

The STLC2500 works with a single clock (sine wave or digital) provided on the RF_CLK_IN pin. Precision

of this clock should be 20 ppm. The external STLC2500 clock could be 13 or 26 MHz (for GSM applica-

tion), 19.2 MHz and 38.4 MHz (for 2.5 & 3G & CDMA platforms).

7.4 Low power clock

The low power clock is used by the baseband part as reference clock during the low power modes. It re-

quires an accuracy of 250ppm. The external STLC2500 clock, provided on the LP_CLK digital pin could

be 3.2 kHz, 16.384 kHz, 32 kHz and 32.768 kHz.

The low power clock must be available at all times.

7.5 Clock detection

The system and low power clocks can be either selected by specific HCI command or by integrated auto-

matic detection algorithm. The clock detection routine steps are:

12/23

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