STLC2500 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STLC2500 Datasheet PDF : 23 Pages
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STLC2500
8 DIGITAL INTERFACES
8.1 The UART interface
The STLC2500 contains a 4-pin (UART_RXD, UART_TXD, UART_RTS, and UART_CTS) UART com-
patible with 16450, 16550 and 16750 standards. It is running up to 1842 kbps (+1.5%/-1%).
The configuration is 8 data bits, 1 start bit, 1 stop bit, and no parity bit. 128-byte FIFO with configurable
threshold interrupts for low CPU load and high throughput. Auto RTS/CTS is implemented in HW, control-
lable by SW.
The UART accepts all HCI commands as described in the Bluetooth specification, it supports H4 propri-
etary commands and the 4-wire UART sleep mode. The complete list of supported proprietary HCI com-
mands is available in the STLC2500 Software Interface document.
Table 20 contains the list of supported baud rates selectable by HCI commands. The default baud rate is
115200 [bps].
Table 20. List of supported baud rates
Baud rate
1842 k
921.6 k
460.8 k
230.4 k
153.6 k
115.2 k (default)
76.8 k
57.6 k
38.4 k
28.8 k
19.2 k
14.4 k
9600
7200
4800
2400
1800
1200
900
600
300
8.2 The PCM interface
The chip contains a 4-pin (PCM_CLK, PCM_SYNC, PCM_A, and PCM_B) direct voice interface to con-
nect to standard CODEC including internal decimator and interpolator filters. The implementation is com-
pliant with the MP-PCM requirements for voice transfer (8 kHz PCM_SYNC and 8 or 16 bits data).
The four signals of the PCM interface are:
– PCM_CLK:
PCM clock
– PCM_SYNC:
PCM 8KHz sync
– PCM_A:
PCM data
– PCM_B:
PCM data
The data can be linear PCM (13-16 bit), µ-Law (8 bit) or A-Law (8bit). The interface can be programmed
as Master or as Slave via specific HCI commands.
Two additional PCM_SYNC signals can be provided via the GPIOs. See section 8.4 for more details.
Figure 5. PCM (A-law, µ-law) standard mode
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
01
15
125 µs
17/23
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