ST7MC1/ST7MC2
Figure
152.
Recommended
CAIN
&
RAIN
4)
values.
1000
Cain 10 nF
100
Cain 22 nF
Cain 47 nF
10
1
0.1
0.01
0.1
1
10
fAIN(KHz)
Figure 153. Typical Application with ADC
VDD
VAIN
VDD
RAIN
AINx
CAIN
0.1µF
VAREF
VSSA
RAREF
VT
0.6V
VT
0.6V
2kΩ(max)
10-Bit A/D
Conversion
IL
±1µA
CADC
6pF
ST7MC
Notes:
1. When VSSA pins are not available on the pinout, the ADC refer to VSS.
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).
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