ST72324J2B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72324J2B5

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Symbol

VIL

VIH

Vhys

VOL

IIO

RON

Parameter

Input low level voltage 1)

Input high level voltage 1)

Schmitt trigger voltage hysteresis 2)

Output low level voltage 3)

Input current on RESET pin

Weak pull-up equivalent resistor

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 4)

tg(RSTL)in Filtered glitch duration 5)

Conditions

Min

Typ

Max

Unit

0.16xVDD V

0.85xVDD

2.5

VDD=5V IIO=+2mA

0.2

0.5

2

TBD

mA

20

External pin

0

Internal reset sources

20

30

120

kΩ

429)

µs

30

429)

µs

2.5

µs

200

ns

Figure 85. Typical Application with RESET pin 6)7)8)

Recommended

if LVD is disabled

VDD

VDD

VDD

ST72XXX

USER

EXTERNAL

RESET

CIRCUIT 5)

0.01µF

4.7kΩ

0.01µF

Required if LVD is disabled

RON

Filter

PULSE

GENERATOR

INTERNAL

RESET

WATCHDOG

LVD RESET

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

the RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-

vironments.

6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 12.9.1 . Otherwise the reset will not be taken into account internally.

8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value

specified for IINJ(RESET) in Section 12.2.2 on page 114.

9. Data guaranteed by design, not tested in production.

138/161

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